This invention relates to an electrostatic protection circuit for use in a semiconductor integrated circuit, such as, an integrated circuit (IC) and a large-scale integrated circuit (LSI).
An electrostatic protection circuit of the type described has been generally used in order to prevent destruction caused by an electrostatic discharge (thereinafter, abbreviated as an ESD) in a semiconductor integrated circuit.
For instance, the conventional electrostatic protection circuit is mainly composed of a P-channel MOS transistor and an N-channel MOS transistor. In this event, these MOS transistors are connected in series to each other. In this condition, the P-channel MOS transistor is connected to a power supply terminal while the N-channel MOS transistor is connected to a ground terminal.
With such a structure, another MOS transistor is often connected to a gate of the above N-channel MOS transistor so as to control a floating state and to reduce a breakdown voltage thereof.
In consequence, the N-channel MOS transistor transfers into a snapback state in order to reduce the EDS pulse which is applied to the gate electrode of the N-channel MOS transistor.
In order to prevent the EDS pulse, the protection transistor must have a large area. Usually, such a protection transistor is structured by a plurality of transistors which are connected in parallel in the electrostatic protection circuit.
However, the breakdown voltages of the protection transistors are fluctuated to one another in the above structure. Consequently, electric charge is concentrated to a specific one of the transistors that has a lowest break down voltage. As a result, the ESD pulse can not be effectively reduced.